1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM). More particularly, the present invention relates to a circuit for calibrating the output driving strength of a DRAM and method thereof.
2. Description of Related Art
With rapid progress in electronic technologies, personal computers have become an indispensable product in our offices and homes. In recent years, the data processing capacity and computational speed of computer equipment are increasing at a tremendous pace. As a result, the hardware devices inside each computer have also undergone revolutionary changes. The memory of a computer have progressed from dynamic random access memory (DRAM), double data rate DRAM (DDR DRAM) to second generation double data rate DRAM (DDRII DRAM). To ensure data transmission integrity in the super-fast DDRII DRAM (operating frequency above 400 MHz), a calibrating mechanism is introduced to correct the output driving strength of the DRAM.
FIG. 1 is a diagram showing a conventional DRAM along with its calibration circuit for calibrating the output driving strength of the DRAM. As shown in FIG. 1, a DRAM 120 comprising a pull-up driving output 121, a pull-down driving output 122 and a driving strength adjusting logic circuit 123 for adjusting the pull-up driving output 121 and the pull-down driving output 122 is provided. An output driving strength calibrating circuit 110 comprising a control logic circuit 111, on-die-termination (ODT) resistors 112 and 113 and high-gain comparators 114 and 115 for calibration is provided to perform a calibration of the output driving strength of the pull-up driving output 121 and the pull-down driving output 122. In addition, an output generator 116 for outputting data (D-out) of the memory control chip and an input comparator 117 for inputting data (D-in) but not for calibration are also shown.
In general, the ODT resistors 112 and 113 have a resistance value of about 300 ohms and the pull-up driving output 121 and the pull-down driving output 122 of he DRAM 120 have a resistance value of about 18 plus or minus 4 ohms. In other words, the resistance of the pull-up and pull-down driving output (121 and 122) ranges from 14 to 22 ohms. In the process of calibrating the pull-up driving output 121, the target resistance of the calibrating pull-up driving output 121 is set to 18 ohms. Hence, the reference voltage Voh received by one input terminal of the high gain comparator 114 is set to 300/(300+18)*Vcc. After comparing with another input terminal E (the calibrating pull-up driving output 121 and the ODT resistor 113 together form a voltage divider), a control signal COUNTP is output to the control logic circuit 111. Thereafter, through the driving strength adjusting logic circuit 123, the calibrating pull-up driving output 121 is adjusted. However, the pull-up driving output 121 can have a resistance value of 18 ohms plus or minus 4 ohms and the ODT resistors 112 and 113 can have a resistance value of 300 ohms. Consequently, the detection window of the high gain comparator 114 falls between −4/(300+18) to +4/(300+18) range. Similarly, in the process of calibrating the pull-down driving output 122, the target resistance of the calibrating pull-down driving output 122 is set to 18 ohms. Hence, the reference voltage Vol received by one input terminal of the high gain comparator 115 is set to 18/(300+18)*Vcc. After comparing with another input terminal E (the calibrating pull-down driving output 122 and the ODT resistor 112 together form a voltage divider), a control signal COUNTN is output to the control logic circuit 111. Thereafter, through the driving strength adjusting logic circuit 123, the calibrating pull-down driving output 122 is adjusted. However, the pull-down driving output 122 can have a resistance value of 18 ohms plus or minus 4 ohms and the ODT resistors 112 and 113 can have a resistance value of 300 ohms. Consequently, the detection window of the high gain comparator 115 falls between −4/(300+18) to +4/(300+18) range.
Because the aforementioned output driving strength calibrating circuit 110 uses the ODT resistors 112 and 113 to carry out the adjustment, the detection window is small when the resistance value is large. In other words, very accurate reference voltages Voh and Vol are required to obtain variation of accuracy of about 1%. Hence, the circuit is more difficult to produce. In addition, high gain comparators capable of resolving a voltage differential less than or equal to 1% must be used. Ultimately, overall production cost of the calibrating circuit is increased significantly.